1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device having a sense circuit utilizing a current-mirror circuit.
2. Description of the Related Art
In circuits provided inside a semiconductor memory device, a plurality of different potentials are generated from an external power supply. Such potentials include the HIGH level and LOW level of word lines, the back-bias level of a memory-cell array portion, the short-circuit level of bit lines, etc. In order to adjust these potentials to desired levels, provision is generally made such that a sense circuit utilizing a current-mirror circuit is used to compare a generated potential with a predetermined reference potential, thereby adjusting the level of the generated potential in response to the outcome of the comparison.
It is necessary for a pair of transistors used in the current-mirror circuit to have identical transistor characteristics so as to increase the accuracy of the generated potential. As the size of devices decreases due to the development of semiconductor technologies, process variation increases, so that variation in characteristics between transistors cannot be avoided even if the transistors are disposed side by side in close proximity.
FIG. 1 is a drawing showing an example of the layout of a related-art current-mirror circuit. The current-mirror circuit of FIG. 1 includes gates 10 and 11, diffusion layers 12A and 12B, diffusion layers 13A and 13B, contacts 14 through 19, power supply lines 20 and 21, and signal lines 22 through 24. The diffusion layers 12A and 12B and the diffusion layers 13A and 13B are formed by diffusing impurity in the semiconductor substrate. The gates 10 and 11 are disposed on the semiconductor substrate via a gate insulating film therebetween. The power supply lines 20 and 21 are arranged in a metal layer, and are connected to the diffusion layers 12A and 13A, respectively, via the respective contacts 14 and 16. The signal lines 22 and 23 are arranged in a metal layer, and are connected to the diffusion layers 12B and 13B, respectively, via the respective contacts 15 and 17. The signal line 24 is arranged in a metal layer, and is connected to the gates 10 and 11 via the respective contacts 18 and 19.
The gate 10 and the diffusion layers 12A and 12B together constitute a first transistor, and the gate 11 and the diffusion layers 13A and 13B together constitute a second transistor. The gate of the first transistor and the gate of the second transistor are both connected to the signal line 24, and the source of the first transistor and the source of the second transistor are both connected to the power supply voltage. Such arrangement forms a current-mirror circuit, in which the same amount of electrical current flows through the first transistor and the second transistor.
In the layout shown in FIG. 1, the power supply nodes are positioned on the same side of the gates so as to achieve the same positional arrangement for the purpose of providing the same transistor characteristics. Further, such a design as to elongate the length of the transistor gates is devised. Since the transistor characteristics vary due to variation in the gate length, the elongation of the gate length can reduce variation in the transistor characteristics by making the variation of the gate length less significant in comparison with the entire length of the gate.
In semiconductor devices, conventionally, LOCOS (local oxidation of silicon) is used for the purpose of device separation. In the LOCOS method, a mask made of a nitride film or the like is formed on a silicon substrate, and an oxide film for the purpose of device separation is formed through thermal oxidation. Due to diffusion occurring during the thermal oxidation, the side of the generated oxide film does not have a steep slope.
In consideration of this, STI (shallow trench isolation) has recently been used for the purpose of device separation in place of LOCOS. In STI, grooves are formed in a silicon substrate through dry etching, and the generated grooves are then filled with oxide films for the purpose of device separation. The oxide films formed through STI have a steep side slope, allowing devices to be densely arranged. STI, however, etches a silicon substrate through dry etching, so that a mechanical stress is generated on the STI interface (i.e., the side wall of a trench) during this process. This stress affects the channel portion of a transistor, thereby changing the mobility of carriers inside the channel. Further, this stress is affected sensitively by the state of the STI interface, and, thus, significantly varies depending on its position.
Because of this, if STI-based oxide films fill the perimeters of the diffusion layers 12A and 12B and the diffusion layers 13A and 13B in the layout of the current-mirror circuit shown in FIG. 1, the channels situated below the gates 10 and 11 are affected near the borders between the diffusion layers 12A and 12B and the oxide films and between the diffusion layers 13A and 13B and the oxide films, resulting in variation in the threshold voltage of transistors. In order to avoid this, it is preferable to refrain from providing a transistor gate near the boarders of a diffusion layer. A contact for a gate, however, is difficult to form at position within a diffusion layer, and thus has to be formed outside the diffusion layer. In the configuration shown in FIG. 1, accordingly, a transistor gate ends up being situated at the borders of a diffusion layer.
FIG. 2 is a drawing showing an example of the layout of a related-art current-mirror circuit that utilizes transistors having a ring-shape gate.
The current-mirror circuit of FIG. 2 includes ring-shape gates 30 and 31, diffusion layers 32A through 32C, contacts 33 through 37, gate extension parts 38 and 39, a power supply line 40, and signal lines 41 and 42. The diffusion layers 32A through 32C are generated by diffusing impurity in a semiconductor substrate. The ring-shape gates 30 and 31 and the gate extension parts 38 and 39 are disposed on the semiconductor substrate via a gate insulating film therebetween. The gate extension parts 38 and 39 are connected to the ring-shape gates 30 and 31, respectively, and serve to extend the ring-shape gates 30 and 31 to the contact position provided outside the diffusion layer 32A.
The power supply line 40 is arranged in a metal layer, and is connected to the diffusion layer 32A via the contact 33. The signal line 41 is arranged in a metal layer, and is connected to the gate extension parts 38 and 39 via the respective contacts 36 and 37.
The signal line 42 is arranged in a metal layer, and is connected to the diffusion layer 32B via the contact 34. The signal line 43 is arranged in a metal layer, and is connected to the diffusion layer 32C via the contact 35.
The ring-shape gate 30 and the diffusion layers 32A and 32B together constitute a first transistor, and the ring-shape gate 31 and the diffusion layers 32A and 32C together constitute a second transistor. The gate of the first transistor and the gate of the second transistor are both connected to the signal line 41, and the source of the first transistor and the source of the second transistor are both comprised of the common diffusion layer 32A, which is connected to the power supply voltage of the power supply line 40. Such arrangement forms a current-mirror circuit, in which the same amount of electrical current flows through the first transistor and the second transistor. The signal line 44 serves to connect the gates of the first and second transistors to the drain of the first transistor, and becomes necessary when the current-mirror circuit of FIG. 2 is used as part of a sense circuit.
In the layout of FIG. 2, the gate extension parts 38 and 39 do not function as transistor gates. This is because both the left-hand side and right-hand side of the gate extension part 38 are the same diffusion layer 32A, and are electrically coupled to the same power supply potential via the power supply line 40. Namely, only the ring-shape gates 30 and 31 function as a transistor gate. Accordingly, even when the perimeter of the diffusion layer 32A is formed by use of an STI structure for the purpose of device isolation, no transistor gate is situated at the STI interface (i.e., at the side wall of a trench), which makes it easier to provide the same transistor characteristics between the first transistor and the second transistor, compared with the configuration shown in FIG. 1.
Even with the configuration shown in FIG. 2, however, there is still the problem of stress in that the transistors are affected by stresses. This is because stresses created during the dry etching process of forming grooves in the silicon substrate have an effect that reaches the position of the ring-shape gates 30 and 31 through the crystal structure. Because of this, the transistor characteristics of each transistor vary depending on the distribution of a stress, the distance from the STI interface, etc.
[Patent Document 1] Japanese Patent Application Publication No. 08-213564
There is thus a need for a semiconductor device that is configurable in such manner that a pair of transistors constituting a current-mirror circuit in a sense circuit has identical characteristics.